ホーム > 小島 拓也/ Kojima, Takuya

小島 拓也

Kojima, Takuya

システム情報系 , 准教授
Institute of Systems and Information Engineering , Associate Professor

https://tkojima.me

オープンアクセス版の論文は「つくばリポジトリ」で読むことができます。
  1. 1. A Decoupled Coarse-Grained Reconfigurable Architecture by Introducing Data Flow Management Unit Ito, Hisako; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
      IEEE International Paralel and Distributed Processing Symposium Workshops (IPDPSW) (2025)
  2. 2. An Acceleration of Homomorphic Encryption for GPUs focusing on Polynomial-graph Ai Nozaki; Takuya Kojima; Hiroshi Nakamura; Hideki Takase
      IEEE Symposium in Low-Power and High-Speed Chips (2025)
  3. 3. A Data Compression Method for DL-SCAs using Denoising Autoencoders Masaki Morita; Takuya Kojima; Haruto Ishii; Hideki TakaseHiroshi Nakamura
      IEEE Symposium in Low-Power and High-Speed Chips (2025)
  4. 4. A Study on Number Theoretic Transform Acceleration on AMD AI Engine Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
      16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2025) (2024)
  5. 5. MLIR-Based Homomorphic Encryption Compiler for GPU Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
      International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2024) (2024)
  6. 6. A Scalable Mapping Method for Elastic CGRAs Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
      2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (2024)
  7. 7. A Data-Flow Visualization for CGRA Debugging Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
      ASPIRE Workshop (2024)
  8. 8. CGRA architecture generation for implementing a systolic array Hajime, Takishita; 小島, 拓也; Hideharu, Amano
      ASPIRE Worhshop (2024)
  9. 9. SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. Takuya Kojima; Yosuke Yanai; Hayate Okuhara; Hideharu Amano (+1 著者) Masahiro Iida
      IEEE Symposium in Low-Power and High-Speed Chips 1 (2024)
  10. 10. Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic. Souhei Takagi; Takuya Kojima; Hideharu Amano; Morihiro KugaMasahiro Iida
      IEICE Transactions on Information & Systems 107: 1476 (2024)
  11. 11. An Area-Efficient Coarse-Grained Reconfigurable Array Design for Approximate Computing Kaito Kutsuna; Takuya Kojima; Hideki Takase; Hiroshi Nakamura
      2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC) 59 (2023)
  12. 12. ILP Based Mapping for Elastic CGRAs Makoto Saito; Takuya Kojima; Hideki Takase; Hiroshi Nakamura
      2023 IEEE 29th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA) (2023)
  13. 13. A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops Aika Kamei; Hideharu Amano; Takuya Kojima; Daiki Yokoyama (+3 著者) Kazuhiro Bessho
      IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31: 1 (2023)
  14. 14. Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC Boma Adhi; Carlos Cortes; Emanuele Del Sozzo; Tomohiro Ueno (+3 著者) Kentaro Sano
      2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023 452 (2023)
  15. 15. Body Bias Control on a CGRA based on Convex Optimization. Takuya Kojima; Hayate Okuhara; Masaaki Kondo; Hideharu Amano
      COOL CHIPS 1 (2022)
  16. 16. Exploration Framework for Synthesizable CGRAs Targeting HPC: Initial Design and Evaluation Boma Adhi; Carlos Cortes; Yiyu Tan; Takuya Kojima (+1 著者) Kentaro Sano
      Proceedings - 2022 IEEE 36th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2022 639 (2022)
  17. 17. An Architecture- Independent CGRA Compiler enabling OpenMP Applications Takuya Kojima; Boma Adhi; Carlos Cortes; Yiyu TanKentaro Sano
      Proceedings - 2022 IEEE 36th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2022 631 (2022)
  18. 18. An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings. Ayaka Ohwada; Takuya Kojima; Hideharu Amano
      PDP 1 (2022)
  19. 19. A Scalable Body Bias Optimization Method Towards Low-Power CGRAs Takuya Kojima; Hayate Okuhara; Masaaki Kondo; Hideharu Amano
      IEEE Micro (2022)
  20. 20. Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage Boma Adhi; Carlos Cortes; Tomohiro Ueno; Yiyu Tan (+2 著者) Kentaro Sano
      FPT 2022 - 21st International Conference on Field-Programmable Technology, Proceedings (2022)
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書籍等出版物情報はまだありません。

  1. 1. A Data-Flow Visualization for CGRA Debugging Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
    ASPIRE Workshop
  2. 2. CGRA architecture generation for implementing a systolic array Hajime, Takishita; 小島, 拓也; Hideharu, Amano
    ASPIRE Worhshop
  3. 3. SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks Kojima, Takuya; Yanai, Yosuke; Okuhara, Hayate; Amano, Hideharu; Kuga, Morihiro; Iida, Masahiro
    IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 27)
  4. 4. A Scalable Mapping Method for Elastic CGRAs Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
    2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
  5. 5. MLIR-Based Homomorphic Encryption Compiler for GPU Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
    International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2024)
  6. 6. A Study on Number Theoretic Transform Acceleration on AMD AI Engine Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
    16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2025)
  7. 7. An Acceleration of Homomorphic Encryption for GPUs focusing on Polynomial-graph Ai, Nozaki; 小島, 拓也; Hiroshi, Nakamura; Hideki, Takase
    IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 28)
  8. 8. A Denoising Preprocess Method for Side-Channel Attacks Using Autoencoders Morita, Masaki; Ishii, Haruto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
    IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2025)
  9. 9. A Decoupled Coarse-Grained Reconfigurable Architecture by Introducing Data Flow Management Unit Ito, Hisako; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
    IEEE International Paralel and Distributed Processing Symposium Workshops (IPDPSW)

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