ホーム > 小島 拓也/ Kojima, Takuya
小島 拓也
Kojima, Takuya
システム情報系 , 准教授 Institute of Systems and Information Engineering , Associate Professor
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オープンアクセス版の論文は「つくばリポジトリ」で読むことができます。
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21.
An Architecture- Independent CGRA Compiler enabling OpenMP Applications
Takuya Kojima; Boma Adhi; Carlos Cortes; Yiyu TanKentaro Sano
Proceedings - 2022 IEEE 36th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2022 631 (2022)
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22.
Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures
Takeharu IKEZOE; Takuya KOJIMA; Hideharu AMANO
IEICE Transactions on Electronics E104.C: 215 (2021)
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23.
3次元積層SiPを用いたマルチコアシステムのためのサイクルアキュレートシミュレータCubeSimの開発
小島, 拓也; 池添, 赳治; 天野, 英晴
電子情報通信学会論文誌D 情報・システム J104-D: 228 (2021)
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24.
3次元積層SiPを用いたマルチコアシステムのためのサイクルアキュレートシミュレータCubeSimの開発
小島拓也; 池添赳治; 天野英晴
IEICE Transactions on Information and Systems J104-D: 228 (2021)
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25.
MENTAI: A Fully Automated CGRA Application Development Environment that Supports Hardware/Software Co-design
Ayaka Ohwada; Takuya Kojima; Hideharu Amano
Proceedings - Synthesis And System Integration of Mixed Information technologies(SASIMI2021) 19: (2021)
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26.
Mapping-aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning
Takuya Kojima; Ayaka Ohwada; Hideharu Amano
IEEE Transactions on Parallel and Distributed Systems 1 (2021)
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27.
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops
Aika Kamei; Takuya Kojima; Hideharu Amano; Daiki Yokoyama (+4 著者) Kazuhiro Bessho
Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021 273 (2021)
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28.
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures
Takuya Kojima; Nguyen Anh Vu Doan; Hideharu Amano
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28: 2383 (2020)
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29.
Compiler Framework for Spatial Mapping CGRA using LLVM
Ayaka Ohwada; Takuya Kojima; Hideharu Amano
Proceedings - IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 23) 1 (2020)
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30.
A coarse-grained reconfigurable architecture with a fault tolerant non-volatile configurable memory
Takeharu Ikezoe; Takuya Kojima; Hideharu Amano
Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019 2019-December: 81 (2019)
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31.
Real chip performance evaluation on through chip interface IP for renesas SOTB 65nm process
Hideto Kayashima; Takuya Kojima; Hayate Okuhara; Tsunaaki ShideiHideharu Amano
Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019 269 (2019)
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32.
A Real chip evaluation of a CNN accelerator SNACC
Ryohei Tomura; Takuya Kojima; Hideharu Amano
Proceedings - Synthesis And System Integration of Mixed Information technologies(SASIMI2019) 62 (2019)
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33.
A Preliminary evaluation of building block computing systems
Sayaka Terashima; Takuya Kojima; Hayate Okuhara; Kazusa Musha (+3 著者) Mitaro Namiki
Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019 312 (2019)
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34.
Demonstration of low power stream processing using a variable pipelined CGRA
Takuya Kojima; Naoki Ando; Yusuke Matsushita; Hideharu Amano
Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019 411 (2019)
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35.
Refinements in Data Manipulation Method for Coarse Grained Reconfigurable Architectures
Takuya Kojima; Hideharu Amano
Proceedings - 2019 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2019 113 (2019)
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36.
A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures
Takuya KOJIMA; Hideharu AMANO
IEICE Transactions on Information and Systems E102.D: 1247 (2019)
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37.
Real Chip Performance Evaluation of Inductive Coupling TCI IP
Hideto Kayashima; Takuya Kojima; Hayate Okuhara; Tsunaaki ShideiHideharu Amano
Proceedings - IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 22) 1 (2019)
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38.
A configuration data multicasting method for coarse-grained reconfigurable architectures
Takuya Kojima; Hideharu Amano
Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018 239 (2018)
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39.
Real chip evaluation of a low power CGRA with optimized application mapping
Takuya Kojima; Naoki Ando; Yusuke Matshushita; Hayate Okuhara (+1 著者) Hideharu Amano
ACM International Conference Proceeding Series (2018)
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40.
Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures
Takuya KOJIMA; Naoki ANDO; Hayate OKUHARA; Ng. Anh Vu DOANHideharu AMANO
IEICE Transactions on Information and Systems E101.D: 1532 (2018)
書籍等出版物情報はまだありません。
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1.
A Data-Flow Visualization for CGRA Debugging
Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
ASPIRE Workshop
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2.
CGRA architecture generation for implementing a systolic array
Hajime, Takishita; 小島, 拓也; Hideharu, Amano
ASPIRE Worhshop
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3.
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks
Kojima, Takuya; Yanai, Yosuke; Okuhara, Hayate; Amano, Hideharu; Kuga, Morihiro; Iida, Masahiro
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 27)
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4.
A Scalable Mapping Method for Elastic CGRAs
Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
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5.
MLIR-Based Homomorphic Encryption Compiler for GPU
Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2024)
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6.
A Study on Number Theoretic Transform Acceleration on AMD AI Engine
Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2025)
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7.
An Acceleration of Homomorphic Encryption for GPUs focusing on Polynomial-graph
Ai, Nozaki; 小島, 拓也; Hiroshi, Nakamura; Hideki, Takase
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 28)
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8.
A Denoising Preprocess Method for Side-Channel Attacks Using Autoencoders
Morita, Masaki; Ishii, Haruto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2025)
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9.
A Decoupled Coarse-Grained Reconfigurable Architecture by Introducing Data Flow Management Unit
Ito, Hisako; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
IEEE International Paralel and Distributed Processing Symposium Workshops (IPDPSW)
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