ホーム > 小島拓也/ Kojima, Takuya

小島拓也

Kojima, Takuya

システム情報系 , 准教授
Institute of Systems and Information Engineering , Associate Professor

https://tkojima.me

21. Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC Boma Adhi; Carlos Cortes; Emanuele Del Sozzo; Tomohiro Ueno (+3 著者) Kentaro Sano
2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023 452 (2023) Semantic Scholar
22. A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops Aika Kamei; Hideharu Amano; Takuya Kojima; Daiki Yokoyama (+3 著者) Kazuhiro Bessho
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31: 1 (2023) Semantic Scholar
23. An Architecture- Independent CGRA Compiler enabling OpenMP Applications Takuya Kojima; Boma Adhi; Carlos Cortes; Yiyu TanKentaro Sano
Proceedings - 2022 IEEE 36th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2022 631 (2022) Semantic Scholar
24. Body Bias Control on a CGRA based on Convex Optimization. Takuya Kojima; Hayate Okuhara; Masaaki Kondo; Hideharu Amano
COOL CHIPS 1 (2022) Semantic Scholar
25. An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings. Ayaka Ohwada; Takuya Kojima; Hideharu Amano
PDP 1 (2022) Semantic Scholar
26. Exploration Framework for Synthesizable CGRAs Targeting HPC: Initial Design and Evaluation Boma Adhi; Carlos Cortes; Yiyu Tan; Takuya Kojima (+1 著者) Kentaro Sano
Proceedings - 2022 IEEE 36th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2022 639 (2022) Semantic Scholar
27. A Scalable Body Bias Optimization Method Towards Low-Power CGRAs Takuya Kojima; Hayate Okuhara; Masaaki Kondo; Hideharu Amano
IEEE Micro (2022) Semantic Scholar
28. The Cost of Flexibility: Embedded versus Discrete Routers in CGRAs for HPC Boma Adhi; Carlos Cortes; Yiyu Tan; Takuya Kojima (+1 著者) Kentaro Sano
Proceedings - IEEE International Conference on Cluster Computing, ICCC 2022-September: 347 (2022) Semantic Scholar
29. Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage Boma Adhi; Carlos Cortes; Tomohiro Ueno; Yiyu Tan (+2 著者) Kentaro Sano
FPT 2022 - 21st International Conference on Field-Programmable Technology, Proceedings (2022) Semantic Scholar
30. Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures Takeharu IKEZOE; Takuya KOJIMA; Hideharu AMANO
IEICE Transactions on Electronics E104.C: 215 (2021) Semantic Scholar
31. 3次元積層SiPを用いたマルチコアシステムのためのサイクルアキュレートシミュレータCubeSimの開発小島, 拓也; 池添, 赳治; 天野, 英晴
電子情報通信学会論文誌D 情報・システム J104-D: 228 (2021)
32. MENTAI: A Fully Automated CGRA Application Development Environment that Supports Hardware/Software Co-design Ayaka Ohwada; Takuya Kojima; Hideharu Amano
Proceedings - Synthesis And System Integration of Mixed Information technologies(SASIMI2021) 19: (2021)
33. 3次元積層SiPを用いたマルチコアシステムのためのサイクルアキュレートシミュレータCubeSimの開発小島拓也; 池添赳治; 天野英晴
IEICE Transactions on Information and Systems J104-D: 228 (2021)
34. Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops Aika Kamei; Takuya Kojima; Hideharu Amano; Daiki Yokoyama (+4 著者) Kazuhiro Bessho
Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021 273 (2021) Semantic Scholar
35. Mapping-aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning Takuya Kojima; Ayaka Ohwada; Hideharu Amano
IEEE Transactions on Parallel and Distributed Systems 1 (2021) Semantic Scholar
36. GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures Takuya Kojima; Nguyen Anh Vu Doan; Hideharu Amano
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28: 2383 (2020) Semantic Scholar
37. Compiler Framework for Spatial Mapping CGRA using LLVM Ayaka Ohwada; Takuya Kojima; Hideharu Amano
Proceedings - IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 23) 1 (2020)
38. A coarse-grained reconfigurable architecture with a fault tolerant non-volatile configurable memory Takeharu Ikezoe; Takuya Kojima; Hideharu Amano
Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019 2019-December: 81 (2019) Semantic Scholar
39. Real chip performance evaluation on through chip interface IP for renesas SOTB 65nm process Hideto Kayashima; Takuya Kojima; Hayate Okuhara; Tsunaaki ShideiHideharu Amano
Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019 269 (2019) Semantic Scholar
40. A Real chip evaluation of a CNN accelerator SNACC Ryohei Tomura; Takuya Kojima; Hideharu Amano
Proceedings - Synthesis And System Integration of Mixed Information technologies(SASIMI2019) 62 (2019)

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1. Computation Platforms for Multi-access Edge Computing Amano, Hideharu; KOJIMA, Takuya; Namiki, Mitaro
Springer Singapore 2025年7月

1. オートエンコーダを活用した前処理による深層学習手法を用いるサイドチャネル攻撃の軽量化森田, 昌樹; 小島, 拓也; 石井, 悠人; 高瀬, 英希; 中村, 宏
HWS研究会
2. 多項式演算グラフに着目したデータ再利用を高めるGPU向け準同型暗号コンパイラ野崎, 愛; 小島, 拓也; 中村, 宏; 高瀬, 英希
第252回システム・アーキテクチャ (ETNET 2025)
3. 回転因子に着目した数論変換のAMD AI Engine向け並列化坪井, 元春; 野崎, 愛; 小島, 拓也; 中村, 宏; 高瀬, 英希
第252回システム・アーキテクチャ (ETNET 2025)
4. 暗号処理向け粗粒度再構成可能アーキテクチャの評価小島, 拓也; 伊藤, 向子
デザインガイア2025 -VLSI設計の新しい大地-
5. デノイジングオートエンコーダを活用したサイドチャネル攻撃のための前処理ノイズ除去手法森田, 昌樹; 小島, 拓也; 高瀬, 英希; 中村, 宏
HWS研究会
6. 制御フロー処理の資源効率化に向けたヘテロジニアスCGRA構成の検討伊藤, 向子; 小島, 拓也; 高瀬, 英希; 中村, 宏
第256回システム・アーキテクチャ (ETNET 2026)
7. AMD AI Engineによる準同型暗号のクライアント処理の高速化片倉, 大翔; 野崎, 愛; 小島, 拓也; 中村, 宏; 高瀬, 英希
第256回システム・アーキテクチャ (ETNET 2026)
8. 準同型暗号のGPUアクセラレーション手法のデータフローに応じた分類と性能分析野崎, 愛; 小島, 拓也; 中村, 宏; 高瀬, 英希
第256回システム・アーキテクチャ (ETNET 2026)
9. Control-Flow Execution on CGRAs: A Comprehensive Survey of Architectural and Compilation Techniques Ito, Hisako; KOJIMA, Takuya; Takase, Hideki; Nakamura, Hiroshi
IEEE International Paralel and Distributed Processing Symposium Workshops (IPDPSW)
10. 防災観測用光伝送システムの長期運用更新に向けたSTMフレーム処理のFPGA実装村上, 祥徳; 杉浦, 圭祐; 小島, 拓也; 山口, 佳樹; 功刀, 卓; 久保, 久彦
電子情報通信学会コミュニケーションシステム研究会 (CS)
11. A Data-Flow Visualization for CGRA Debugging Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
ASPIRE Workshop
12. CGRA architecture generation for implementing a systolic array Hajime, Takishita; 小島, 拓也; Hideharu, Amano
ASPIRE Worhshop
13. SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks Kojima, Takuya; Yanai, Yosuke; Okuhara, Hayate; Amano, Hideharu; Kuga, Morihiro; Iida, Masahiro
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 27)
14. A Scalable Mapping Method for Elastic CGRAs Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
15. MLIR-Based Homomorphic Encryption Compiler for GPU Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2024)
16. A Study on Number Theoretic Transform Acceleration on AMD AI Engine Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2025)
17. An Acceleration of Homomorphic Encryption for GPUs focusing on Polynomial-graph Ai, Nozaki; 小島, 拓也; Hiroshi, Nakamura; Hideki, Takase
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 28)
18. A Denoising Preprocess Method for Side-Channel Attacks Using Autoencoders Morita, Masaki; Ishii, Haruto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2025)
19. A Decoupled Coarse-Grained Reconfigurable Architecture by Introducing Data Flow Management Unit Ito, Hisako; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
IEEE International Paralel and Distributed Processing Symposium Workshops (IPDPSW)

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