ホーム > 小島拓也/ Kojima, Takuya

小島拓也

Kojima, Takuya

システム情報系 , 准教授
Institute of Systems and Information Engineering , Associate Professor

https://tkojima.me

41. Compiler Framework for Spatial Mapping CGRA using LLVM Ayaka Ohwada; Takuya Kojima; Hideharu Amano
Proceedings - IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 23) 1 (2020)
42. A coarse-grained reconfigurable architecture with a fault tolerant non-volatile configurable memory Takeharu Ikezoe; Takuya Kojima; Hideharu Amano
Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019 2019-December: 81 (2019) Semantic Scholar
43. Real chip performance evaluation on through chip interface IP for renesas SOTB 65nm process Hideto Kayashima; Takuya Kojima; Hayate Okuhara; Tsunaaki ShideiHideharu Amano
Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019 269 (2019) Semantic Scholar
44. A Real chip evaluation of a CNN accelerator SNACC Ryohei Tomura; Takuya Kojima; Hideharu Amano
Proceedings - Synthesis And System Integration of Mixed Information technologies(SASIMI2019) 62 (2019)
45. A Preliminary evaluation of building block computing systems Sayaka Terashima; Takuya Kojima; Hayate Okuhara; Kazusa Musha (+3 著者) Mitaro Namiki
Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019 312 (2019) Semantic Scholar
46. Demonstration of low power stream processing using a variable pipelined CGRA Takuya Kojima; Naoki Ando; Yusuke Matsushita; Hideharu Amano
Proceedings - 29th International Conference on Field-Programmable Logic and Applications, FPL 2019 411 (2019) Semantic Scholar
47. A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures Takuya KOJIMA; Hideharu AMANO
IEICE Transactions on Information and Systems E102.D: 1247 (2019) Semantic Scholar
48. Refinements in Data Manipulation Method for Coarse Grained Reconfigurable Architectures Takuya Kojima; Hideharu Amano
Proceedings - 2019 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2019 113 (2019) Semantic Scholar
49. Real Chip Performance Evaluation of Inductive Coupling TCI IP Hideto Kayashima; Takuya Kojima; Hayate Okuhara; Tsunaaki ShideiHideharu Amano
Proceedings - IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 22) 1 (2019)
50. A configuration data multicasting method for coarse-grained reconfigurable architectures Takuya Kojima; Hideharu Amano
Proceedings - 2018 International Conference on Field-Programmable Logic and Applications, FPL 2018 239 (2018) Semantic Scholar
51. Real chip evaluation of a low power CGRA with optimized application mapping Takuya Kojima; Naoki Ando; Yusuke Matshushita; Hayate Okuhara (+1 著者) Hideharu Amano
ACM International Conference Proceeding Series (2018) Semantic Scholar
52. Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures Takuya KOJIMA; Naoki ANDO; Hayate OKUHARA; Ng. Anh Vu DOANHideharu AMANO
IEICE Transactions on Information and Systems E101.D: 1532 (2018) Semantic Scholar
53. Scalable deep neural network accelerator cores with cubic integration using through chip interface Ryuichi Sakamoto; Ryo Takata; Jun Ishii; Masaaki Kondo (+3 著者) Hideharu Amano
Proceedings - International SoC Design Conference 2017, ISOCC 2017 155 (2018) Semantic Scholar
54. A micro-controller for MTJ-based Non-volatile Flip-flops for data verification Takeharu Ikezoe; Takuya Kojima; Hideharu Amano; Junya Akaike (+3 著者) Kojiro Yagami
Proceedings - IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 21) 1 (2018)
55. The design and implementation of scalable deep neural network accelerator cores Ryuichi Sakamoto; Ryo Takata; Jun Ishii; Masaaki Kondo (+3 著者) Hideharu Amano
Proceedings - IEEE 11th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2017 2018-January: 13 (2018) Semantic Scholar
56. A shared memory chip for twin-tower of chips Sayaka Terashima; Takuya Kojima; Hayate Okuhara; Yusuke Matsushita (+2 著者) Hideharu Amano
Proceedings - Synthesis And System Integration of Mixed Information technologies(SASIMI2018) 353 (2018)
57. Glitch-aware variable pipeline optimization for CGRAs Takuya Kojima; Naoki Ando; Hayate Okuhara; Hideharu Amano
2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017 2018-January: 1 (2018) Semantic Scholar
58. Body bias optimization for variable pipelined CGRA Takuya Kojima; Naoki Ando; Hayate Okuhara; Ng Anh Vu DoanHideharu Amano
2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017 (2017) Semantic Scholar
59. Power Optimization for CGRA with Control of Variable Pipeline and Body Bias Voltage Takuya Kojima; Naoki Ando; Hayate Okuhara; Ng. Anh Vu DoanHideharu Amano
Proceedings - IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 20) 1 (2017)

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1. Computation Platforms for Multi-access Edge Computing Amano, Hideharu; KOJIMA, Takuya; Namiki, Mitaro
Springer Singapore 2025年7月

1. Dataflow-Oriented Classification and Performance Analysis of GPU-Accelerated Homomorphic Encryption KOJIMA, Takuya; Nozaki, Ai
The 50th IEEE International Conference on Computers, Software, and Applications (COMPSAC 2026)
2. Unsupervised Anomaly Detection for Event Cameras with Lightweight Spatio-Temporal Encoder on FPGA Yang, Hui; Sugiura, Keisuke; Kojima, Takuya; Yamaguchi, Yoshiki
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)
3. AIE-HE: Accelerating Client-Side Processing of Homomorphic Encryption on AMD AI Engine KOJIMA, Takuya; Haruto, Katakura
The 55th International Conference on Parallel Processing (ICPP 2026)
4. Lightweight Adjacency Estimation for Irregular Object Reassembly using Siamese Networks Kodama, Kokoro; Sugiura, Keisuke; Kojima, Takuya; Yamaguchi, Yoshiki
International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)
5. オートエンコーダを活用した前処理による深層学習手法を用いるサイドチャネル攻撃の軽量化森田, 昌樹; 小島, 拓也; 石井, 悠人; 高瀬, 英希; 中村, 宏
HWS研究会
6. 多項式演算グラフに着目したデータ再利用を高めるGPU向け準同型暗号コンパイラ野崎, 愛; 小島, 拓也; 中村, 宏; 高瀬, 英希
第252回システム・アーキテクチャ (ETNET 2025)
7. 回転因子に着目した数論変換のAMD AI Engine向け並列化坪井, 元春; 野崎, 愛; 小島, 拓也; 中村, 宏; 高瀬, 英希
第252回システム・アーキテクチャ (ETNET 2025)
8. 暗号処理向け粗粒度再構成可能アーキテクチャの評価小島, 拓也; 伊藤, 向子
デザインガイア2025 -VLSI設計の新しい大地-
9. デノイジングオートエンコーダを活用したサイドチャネル攻撃のための前処理ノイズ除去手法森田, 昌樹; 小島, 拓也; 高瀬, 英希; 中村, 宏
HWS研究会
10. 制御フロー処理の資源効率化に向けたヘテロジニアスCGRA構成の検討伊藤, 向子; 小島, 拓也; 高瀬, 英希; 中村, 宏
第256回システム・アーキテクチャ (ETNET 2026)
11. AMD AI Engineによる準同型暗号のクライアント処理の高速化片倉, 大翔; 野崎, 愛; 小島, 拓也; 中村, 宏; 高瀬, 英希
第256回システム・アーキテクチャ (ETNET 2026)
12. 準同型暗号のGPUアクセラレーション手法のデータフローに応じた分類と性能分析野崎, 愛; 小島, 拓也; 中村, 宏; 高瀬, 英希
第256回システム・アーキテクチャ (ETNET 2026)
13. Control-Flow Execution on CGRAs: A Comprehensive Survey of Architectural and Compilation Techniques Ito, Hisako; KOJIMA, Takuya; Takase, Hideki; Nakamura, Hiroshi
IEEE International Paralel and Distributed Processing Symposium Workshops (IPDPSW)
14. 防災観測用光伝送システムの長期運用更新に向けたSTMフレーム処理のFPGA実装村上, 祥徳; 杉浦, 圭祐; 小島, 拓也; 山口, 佳樹; 功刀, 卓; 久保, 久彦
電子情報通信学会コミュニケーションシステム研究会 (CS)
15. A Data-Flow Visualization for CGRA Debugging Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
ASPIRE Workshop
16. CGRA architecture generation for implementing a systolic array Hajime, Takishita; 小島, 拓也; Hideharu, Amano
ASPIRE Worhshop
17. SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks Kojima, Takuya; Yanai, Yosuke; Okuhara, Hayate; Amano, Hideharu; Kuga, Morihiro; Iida, Masahiro
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 27)
18. A Scalable Mapping Method for Elastic CGRAs Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
19. MLIR-Based Homomorphic Encryption Compiler for GPU Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2024)
20. A Study on Number Theoretic Transform Acceleration on AMD AI Engine Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2025)