ホーム > 小島 拓也/ Kojima, Takuya
小島 拓也
Kojima, Takuya
システム情報系 , 准教授 Institute of Systems and Information Engineering , Associate Professor
関連記事はまだありません。
オープンアクセス版の論文は「つくばリポジトリ」で読むことができます。
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41.
A shared memory chip for twin-tower of chips
Sayaka Terashima; Takuya Kojima; Hayate Okuhara; Yusuke Matsushita (+2 著者) Hideharu Amano
Proceedings - Synthesis And System Integration of Mixed Information technologies(SASIMI2018) 353 (2018)
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42.
Glitch-aware variable pipeline optimization for CGRAs
Takuya Kojima; Naoki Ando; Hayate Okuhara; Hideharu Amano
2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2017 2018-January: 1 (2018)
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43.
Body bias optimization for variable pipelined CGRA
Takuya Kojima; Naoki Ando; Hayate Okuhara; Ng Anh Vu DoanHideharu Amano
2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017 (2017)
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44.
Power Optimization for CGRA with Control of Variable Pipeline and Body Bias Voltage
Takuya Kojima; Naoki Ando; Hayate Okuhara; Ng. Anh Vu DoanHideharu Amano
Proceedings - IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 20) 1 (2017)
書籍等出版物情報はまだありません。
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1.
A Data-Flow Visualization for CGRA Debugging
Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
ASPIRE Workshop
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2.
CGRA architecture generation for implementing a systolic array
Hajime, Takishita; 小島, 拓也; Hideharu, Amano
ASPIRE Worhshop
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3.
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks
Kojima, Takuya; Yanai, Yosuke; Okuhara, Hayate; Amano, Hideharu; Kuga, Morihiro; Iida, Masahiro
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 27)
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4.
A Scalable Mapping Method for Elastic CGRAs
Saito, Makoto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
2024 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
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5.
MLIR-Based Homomorphic Encryption Compiler for GPU
Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART2024)
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6.
A Study on Number Theoretic Transform Acceleration on AMD AI Engine
Nozaki, Ai; Kojima, Takuya; Nakamura, Hiroshi; Takase, Hideki
16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2025)
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7.
An Acceleration of Homomorphic Encryption for GPUs focusing on Polynomial-graph
Ai, Nozaki; 小島, 拓也; Hiroshi, Nakamura; Hideki, Takase
IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS 28)
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8.
A Denoising Preprocess Method for Side-Channel Attacks Using Autoencoders
Morita, Masaki; Ishii, Haruto; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2025)
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9.
A Decoupled Coarse-Grained Reconfigurable Architecture by Introducing Data Flow Management Unit
Ito, Hisako; Kojima, Takuya; Takase, Hideki; Nakamura, Hiroshi
IEEE International Paralel and Distributed Processing Symposium Workshops (IPDPSW)
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