ホーム > 西川 博昭/ Nishikawa, Hiroaki

西川 博昭

Nishikawa, Hiroaki

筑波大学 , 名誉教授
University of Tsukuba , Professor Emeritus

http://www.ddna.cs.tsukuba.ac.jp/index.html

オープンアクセス版の論文は「つくばリポジトリ」で読むことができます。
  1. 1. FPGA-oriented Two-phase Bundled-data Circular Self-timed Pipeline YOSHIKAWA, Senri; SANNOMIYA, Shuji; IWATA, Makoto; NISHIKAWA, Hiroaki
      2024 Twelfth International Symposium on Computing and Networking (CANDAR) 125 (2024)
  2. 2. FPGA向け二相束データ式 環状自己同期型パイプライン回路 木下, 優; 三宮, 秀次; 吉川, 千里; 岩田, 誠西川, 博昭
      情報処理学会研究報告 Vol.2023-ARC-255: 1 (2023)
  3. 3. EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline Senri Yoshikawa; Shuji Sannomiya; Makoto Iwata; Akira SatoHiroaki Nishikawa
      Journal of Information Processing 31: 495 (2023) Semantic Scholar
  4. 4. Pipeline Stage Level Simulation Method for Self-Timed Data-Driven Processor on FPGA Yoshikawa, Senri; Sannomiya, Shuji; Iwata, Makoto; Nishikawa, Hiroaki
      Proceedings of International Electrical Engineering Congress (iEECON2020) (2020)
  5. 5. Data-Driven IoT Platform Architecture with Overload Avoidance Capability Sannomiya, Shuji; Nishida, Yukikuni; Nishikawa, Hiroaki
      Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'18) 262 (2018)
  6. 6. Abnormal Traffic Detection Circuit with Real-time Cardinality Counter Sannomiya, Shuji; Sato, Akira; 吉田, 健一; Nishikawa, Hiroaki
      JIP(Journal Information Processing) 26: 590 (2018) Semantic Scholar
  7. 7. Cardinality Counting Circuit for Real-Time Abnormal Traffic Detection Shuji Sannomiya; Akira Sato; Kenichi Yoshida; Hiroaki Nishikawa
      Proceedings - International Computer Software and Applications Conference 1: 505 (2017) Semantic Scholar
  8. 8. FPGA Implementation of Cardinality-Based Abnormal Traffic Detection Algorithm Sannomiya, Shuji; Sato, Akira; Yoshida, Kenichi; Nishikawa, Hiroaki
      Proceedings of the 2017 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’17) 252 (2017)
  9. 9. FPGA Implementation of Cardinality-Based Abnormal Traffic Detection Algorithm Sannomiya, Shuji; Sato, Akira; Yoshida, Kenichi; Nishikawa, Hiroaki
      Proceedings of International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'17) 252 (2017)
  10. 10. トリリオンセンサユニバースを実現するデータ駆動プロセッサ 西川博昭
      The Institute of Electronics, Information and Communication Engineers, IEICE Technical Report 116: 139 (2016)
  11. 11. Data-Driven Sensor Networking Processor Tolerating Instantaneously Excessive Load Sannomiya, Shuji; Nishida, Yukikuni; Iwata, Makoto; Nishikawa, Hiroaki
      Proceedings of the 2016 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’16) 316 (2016)
  12. 12. Greedy Forwarding Prolonging the Network Lifetime Based on Two-hop Information over MANET Phonepadith,Phounmmavong; Keisuke,Utsu; Chee,Onn Chow; Nishikawa,HiroakiHiroshi,Ishii
      Proceedings of the 2016 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’16) 303 (2016)
  13. 13. Broadcast-based information sharing system (BBISS) on wireless ad hoc communication environment Keisuke Utsu; Chee Onn Chow; Hiroaki Nishikawa; Hiroshi Ishii
      JOURNAL OF SUPERCOMPUTING 72: 1399 (2016) Semantic Scholar
  14. 14. Efficient Location-aided Route Discovery Mechanism for Ad-hoc networks Phonepadith,Phounmmavong; Keisuke,Utsu; Hiroaki,Nishikawa; Hiroshi,Ishii
      Proceedings of the 2015 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’15) 551 (2015)
  15. 15. Data-Driven Sensor Networking System Simulator Kazuhiro,Aoki; Shuji,Sannomiya; Nishikawa,Hiroaki
      Proceedings of the 2015 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’15) 564 (2015)
  16. 16. Highly-Dependable and Long-Lifetime Data-Driven Networking Processor with Energy Assurance Capability Shuji,Sannomiya; Nishikawa,Hiroaki
      Proceedings of the 2015 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’15) 557 (2015)
  17. 17. 細粒度パワーゲーティング機構を備えた自己同期型パイプラインとその実装評価 宮城桂; 岩田誠; 三宮秀次; 西川博昭
      The Institute of Electronics, Information and Communication Engineers Vol.J97-A: 554 (2014)
  18. 18. A Novel Information Sharing Architecture Constructed by Broadcast Based Information Sharing System (BBISS) Keisuke,Utsu; Chee,Onn Chow; Nishikawa,Hiroaki; Hiroshi,Ishii
      Proceedings of the 2014 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’14) 534 (2014)
  19. 19. A Safety Information Sharing Application on BBISS Tomomi,Itoh; Ayami,Manaka; Yuuka,Sugawara; Hiroshi,Ishii (+1 著者) Keisuke,Utsu
      Proceedings of the 2014 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’14) 490 (2014)
  20. 20. An optimization study on Broadcast Based Information Sharing System (BBISS) Sayuri,Wada; Hiroshi,Ishii; Nishikawa,Hiroaki; Keisuke,Utsu
      Proceedings of the 2014 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’14) 485 (2014)
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  1. 1. IoT/CPS/M2M応用市場とデバイス・材料技術 西川博昭 (担当:分担執筆, 範囲:センサネットワークの超低消費電力化)
    S＆T出版株式会社 2015年4月 (ISBN: 9784907002442)
  2. 2. Albex Publishing Corporation Hiroaki, Terada; Hiroaki, Nishikawa; Katsuhiko, Asada; Satoshi, Matsumoto; Souichi, Miyata; Shinji, Komori; Kenji, Shima (担当:分担執筆, 範囲:VLSI Design of a One-Chip Data-Driven Processor: Q-v1)
    Data Flow Computing: Theory and Practice, Chapter 17, Ablex Publishing Corporation 1992年5月
  3. 3. ビジュアル・プログラミング 西川博昭 (担当:単訳)
    日経ＢＰ社 1991年6月
  4. 4. オペレーティング・システムの論理設計 西川博昭
    日経ＢＰ社 1989年4月
  5. 5. 並列コンピュータ・アーキテクチャ 寺田浩詔; 西川博昭
    共立出版 1989年3月
  1. 1. FPGA向き自己同期型パイプライン回路構成法 吉川, 千里; 三宮, 秀次; 岩田, 誠; 佐藤, 聡; 西川, 博昭
    第235回ARC・第193回SLDM合同研究発表会 2021年1月25日
  2. 2. Pipeline Stage Level Simulation Method for Self-Timed Data-Driven Processor on FPGA Yoshikawa, Senri; Sannomiya, Shuji; Iwata, Makoto; Nishikawa, Hiroaki
    2020 8th International Electrical Engineering Congress (iEECON2020) 2020年3月4日
  3. 3. Data-Driven IoT Platform Architecture with Overload Avoidance Capability Sannomiya, Shuji; Nishida, Yukikuni; Nishikawa, Hiroaki
    The 2018 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'18) 2018年7月30日
  4. 4. FPGA Implementation of Cardinality-Based Abnormal Traffic Detection Algorithm Sannomiya, Shuji; Sato, Akira; Yoshida, Kenichi; Nishikawa, Hiroaki
    PDPTA'17 - The 23rd Int'l Conf on Parallel and Distributed Processing Techniques and Applications 2017年7月17日
  5. 5. Cardinality Counting Circuit for Real-time Abnormal Traffic Detection SANNOMIYA, Shuji; SATO, Akira; Yoshida, Kenichi; NISHIKAWA, Hiroaki
    COMPSAC 2017 2017年7月4日 IEEE CS
  6. 6. Highly-Dependable and Long-Lifetime Data-Driven Networking Processor with Energy Assurance Capability Shuji, Sannomiya; Nishikawa, Hiroaki
    PDPTA'15 - The 21st International Conference on Parallel and Distributed Processing Techniques and Applications 2015年7月27日
  7. 7. Energy Efficient Data-Driven Networking Processor with Autonomous Load Distribution Capability Shuji, Sannomiya; Nishikawa, Hiroaki
    PDPTA'14 - The 2014 International Conference on Parallel and Distributed Processing Techniques and Applications 2014年7月21日
  8. 8. Chip Multiprocessor Platform for Ultra-Low-Power Data-Driven Networking System: ULP-DDNS Shuji, Sannomiya; Ryotaro, Kuroda; Kazuhiro, Aoki; Kei, Miyagi; Makoto, Iwata; Hiroaki, Nishikawa
    The 2011 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'11) 2011年7月18日
  9. 9. Self-Timed Power-Aware Pipeline Chip and Its Evaluation Kei, Miyagi; Shuji, Sannomiya; Makoto, Iwata; Hiroaki, Nishikawa
    The 2011 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA'11) 2011年7月18日
  10. 10. Performance Estimation and Power Minimizing Scheme for a Mobile Ad hoc Networking Node Ben, Abderrazak Jihane; Nishida, Yukikuni; Nishikawa, Hiroaki
    The first International Conference on Communications and Networking (ComNet'09) 2009年11月3日
  11. 11. Performance Estimation and Power Minimizing Scheme for a Mobile Ad hoc Networking Node Ben,Abderrazak Jihane; Nishida,Yukikuni; Nishikawa,Hiroaki
    1st International Conference on Communications and Networking 2009年11月
  12. 12. Architecture of a VLSI-Oriented Data-Driven Processor: the Q-v1 Hiroaki,Nishikawa; Hiroaki,Terada; Shinji,Komori; Kenji,Shima; Toshiya,Okamoto; Souichi,Miyata
    The 1st International Data-Flow Workshop, ACM 1991年1月
  13. 13. FPGA-oriented Two-phase Bundled-data Circular Self-timed Pipeline YOSHIKAWA, Senri; SANNOMIYA, Shuji; IWATA, Makoto; NISHIKAWA, Hiroaki
    2024 Twelfth International Symposium on Computing and Networking (CANDAR)
  14. 14. FPGA向け二相束データ式 環状自己同期型パイプライン回路 木下, 優; 三宮, 秀次; 吉川, 千里; 岩田, 誠; 西川, 博昭
    情報処理学会システム・アーキテクチャ研究会（ARC247）

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