ホーム > 金澤 健治/ Kanazawa, Kenji

金澤 健治

Kanazawa, Kenji

システム情報系
Faculty of Engineering,Information and Systems

オープンアクセス版の論文は「つくばリポジトリ」で読むことができます。
  1. 1. Solving Maximum Clique Problems using FPGA Based on Swap-Based Tabu Search
      HSI-2020 (2021)
  2. 2. Accelerating Swap-Based Tabu Search for Solving Maximum Clique Problems on FPGA 金澤 健治
      ISPA-2019 (2019)
  3. 3. ``FPGA Acceleration to Solve Maximum Clique Problems Encoded into Partial MaxSAT'' Kenji Kanazawa; Shaowei Cai
      MCSoC-2018 217 (2018)
  4. 4. ``Acceleration of Solving Quadratic Assignment Problems on Programmable SoC using High Level Synthesis'' Kenji Kanazawa
      FSP-2017 40 (2017)
  5. 5. An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA Kenji Kanazawa; Tsutomu Maruyama
      IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS E100D: 1807 (2017) Semantic Scholar
  6. 6. ``FPGAを用いた画像処理応用のためのMonotone Chainアルゴリズムの高速計算'' 監物 香保里; 金澤 健治; 森 大和; 相部 範之安永 守利
      電子情報通信学会論文誌 J100-D: 1 (2017)
  7. 7. An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search. Shohei Sassa; Kenji Kanazawa; Shaowei Cai; Moritoshi Yasunaga
      SIGARCH Computer Architecture News 44: 32 (2016) Semantic Scholar
  8. 8. High-speed calculation of convex hull in 2D images using FPGA Kenji Kanazawa; Kahori Kemmotsu; Yamato Mori; Noriyuki AibeMoritoshi Yasuanga
      Advances in Parallel Computing 27: 533 (2016) Semantic Scholar
  9. 9. FPGA acceleration of SAT/Max-SAT solving using variable-way cache Kenji Kanazawa; Tsutomu Maruyama
      Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 1 (2014) Semantic Scholar
  10. 10. "Decoupling-capacitor Allocation Problem Solved by Genetic Algorithm" Kazuma Shibasaka; Kenji Kanazawa; Moritoshi Yasunaga
      EDAPS-2013 1 (2013) Semantic Scholar
  11. 11. "Signal Integrity Evaluation of Segmental Transmission Line under Real-world Application" Hidefumi Inoue; Moritoshi Yasunaga; Kenji Kanazawa; Noriyuki Aibe
      EDAPS-2013 1 (2013)
  12. 12. "Crosstalk-noise Reduction in GHz Domain Using Segmental Transmission Line" Katsuyuki Seki; Kenji Kanazawa; Moritoshi Yasunaga
      EDAPS-2013 1 (2013) Semantic Scholar
  13. 13. Solving SAT-encoded formal verification problems on SoC based on a WSAT algorithm with a new heuristic for hardware acceleration Kenji Kanazawa; Tsutomu Maruyama
      Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013 101 (2013) Semantic Scholar
  14. 14. An FPGA solver for SAT-encoded formal verification problems Kenji Kanazawa; Tsutomu Maruyama
      Proceedings - 21st International Conference on Field Programmable Logic and Applications, FPL 2011 38 (2011) Semantic Scholar
  15. 15. An Approach for Solving Large SAT Problems on FPGA Kenji Kanazawa; Tsutomu Maruyama
      ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 4: 10:1-10:21 (2010) Semantic Scholar
  16. 16. ``FPGAを用いた大規模な充足可能性問題の高速計算'' 金沢 健治; 丸山 勉
      電子情報通信学会論文誌 J90-D: 2713 (2007)
  17. 17. An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma. Yoshiki Yamaguchi; Kenji Kanazawa; Yoshiharu Ohke; Tsutomu Maruyama
      Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007. 358 (2007) Semantic Scholar
  18. 18. An FPGA solver for very large sat problems Kenji Kanazawa; Tsutomu Maruyama
      2007 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLS 1 AND 2 493 (2007) Semantic Scholar
  19. 19. ``FPGAを用いたWSATアルゴリズムの高速計算'' 金沢 健治; 丸山 勉
      電子情報通信学会論文誌 J89-D: 1173 (2006)
  20. 20. An FPGA Solver for Large SAT Problems. Kenji Kanazawa; Tsutomu Maruyama
      Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006 1 (2006) Semantic Scholar
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